Digital ASIC Design and Verification enthusiast, focusing on back-end Physical Design.

Skills:
• EDA Tools : Cadence NCLaunch, Cadence Genus, Cadence Tempus, Cadence Innovus, Cadence
Virtuoso, Xilinx ISE, ModelSim
• Hardware Description Languages : Verilog, VHDL
• Scripting Languages : TCL
• Hardware Platforms : Artrix-7 Nexys-4 DDR FPGA
• Operating System : Linux, Windows
• Software Packages : Microsoft Office Suite